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| 1. general description the pca85262 is a peripheral device which interfaces to almost any liquid crystal display (lcd) 1 with low multiplex rates. it generates the drive signals for any static or multiplexed lcd containing up to four backplanes and up to 32 segments. it can be easily cascaded for larger lcd applications. t he pca85262 is compatible with most microcontrollers and communicates via the two-line bidirectional i 2 c-bus. communication overheads are minimized by a display ram with auto-incremented addressing, by hardware subaddressing, and by display memory switching (static and duplex drive modes). for a selection of nxp lcd segment drivers, see table 24 on page 46 . 2. features and benefits ? aec-q100 grade 2 compliant for automotive applications ? single chip lcd controller and driver ? selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing ? selectable display bias configuration: static, 1 2 , or 1 3 ? internal lcd bias generation with voltage-follower buffers ? 32 segment drives: ? up to 16 7-segment numeric characters ? up to 8 14-segment alphanumeric characters ? any graphics of up to 128 elements ? 32 ? 4-bit ram for display data storage ? display memory bank switching in static and duplex drive modes ? versatile blinking modes ? independent supplies possible for lcd and logic voltages ? wide power supply range: from 1.8 v to 5.5 v ? wide logic lcd supply range: ? from 2.5 v for low-threshold lcds ? up to 8.0 v for guest-host lcds and high-threshold twisted nematic lcds ? low power consumption ? extended temperature range up to 105 ? c ? 400 khz i 2 c-bus interface ? no external components required ? manufactured in silicon gate cmos process pca85262 32 x 4 automotive lcd driver for low multiplex rates rev. 1 ? 11 february 2014 product data sheet 1. the definition of the abbreviations and acronyms used in this data sheet can be found in section 22 .
pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 2 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates 3. ordering information 3.1 ordering options 4. marking table 1. ordering information type number package name description version PCA85262ATT tssop48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm sot362-1 table 2. ordering options product type number sales item (12nc) orderable part number ic revision delivery form PCA85262ATT/a 935303863118 PCA85262ATT/aj 1 tape and reel, 13 inch table 3. marking codes product type number marking code PCA85262ATT pca85262tt pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 3 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates 5. block diagram fig 1. block diagram of pca85262 d d d & / . 6 < 1 & 2 6 & 6 & / 6 $ % 3 9 ' ' % 3 % 3 % 3 6 w r 6 $ $ $ 3 & $ ' , 6 3 / $ < 5 $ 0 ' , 6 3 / $ < 6 ( * 0 ( 1 7 2 8 7 3 8 7 6 ' , 6 3 / $ < 5 ( * , 6 7 ( 5 2 8 7 3 8 7 % $ 1 . 6 ( / ( & 7 $ 1 ' % / , 1 . & 2 1 7 5 2 / ' , 6 3 / $ < & 2 1 7 5 2 / / ( 5 % $ & . 3 / $ 1 ( 2 8 7 3 8 7 6 / & ' 9 2 / 7 $ * ( 6 ( / ( & 7 2 5 / & ' % , $ 6 * ( 1 ( 5 $ 7 2 5 & / 2 & . 6 ( / ( & 7 $ 1 ' 7 , 0 , 1 * % / , 1 . ( 5 7 , 0 ( % $ 6 ( 2 6 & , / / $ 7 2 5 & 2 0 0 $ 1 ' ' ( & 2 ' ( 5 : 5 , 7 ( ' $ 7 $ & 2 1 7 5 2 / ' $ 7 $ 3 2 , 1 7 ( 5 $ 1 ' $ 8 7 2 , 1 & 5 ( 0 ( 1 7 , 1 3 8 7 ) , / 7 ( 5 6 , & % 8 6 & 2 1 7 5 2 / / ( 5 6 8 % $ ' ' 5 ( 6 6 & 2 8 1 7 ( 5 6 ' $ 9 6 6 9 / & ' pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 4 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates 6. pinning information 6.1 pinning 6.2 pin description top view. for mechanical details, see figure 28 . fig 2. pinning diagram for PCA85262ATT (tssop48) 3 & $ $ 7 7 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 ' $ 6 6 & / 6 6 < 1 & 6 & / . 6 9 ' ' 6 2 6 & 6 $ 6 $ 6 $ 6 6 $ 6 9 6 6 6 9 / & ' 6 % 3 6 % 3 6 % 3 % 3 d d d table 4. pin description of PCA85262ATT (tssop48) input or input/output pins must always be at a defined level (v ss or v dd ) unless otherwise specified. symbol pin type description sda 10 input/output i 2 c-bus serial data line scl 11 input i 2 c-bus serial clock sync 12 input/output cascade synchronization clk 13 input/output clock line v dd 14 supply supply voltage osc 15 input internal oscillator enable a0 to a2 16 to 18 input subaddress inputs sa0 19 input i 2 c-bus address input v ss 20 supply ground supply voltage pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 5 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates 7. functional description the pca85262 is a versatile peripheral de vice designed to interface between any microcontroller to a wide variety of lcd segm ent or dot-matrix displays. it can directly drive any static or multiplexed lcd contai ning up to four backplanes and up to 32 segments. 7.1 commands of pca85262 the commands available to the pca85262 are defined in ta b l e 5 . all available commands carry a continuation bit c in their most significant bit position as shown in figure 21 . when this bit is set logic 1, it indicates that the next byte of the transfer to arrive will also repr esent a command. if this bit is set logic 0, it indicates that the command byte is the last in the transfer. further bytes are regarded as display data (see table 6 ). 7.1.1 command: mode-set the mode-set command allows configuring the multiplex mode, the bias levels and enabling or disabling the display. v lcd 21 supply lcd supply voltage bp0 to bp3 22 to 25 output lcd backplane outputs s0 to s22, s23 to s31 26 to 48, 1 to 9 output lcd segment outputs table 4. pin description of PCA85262ATT (tssop48) ?continued input or input/output pins must always be at a defined level (v ss or v dd ) unless otherwise specified. symbol pin type description table 5. definition of the pca85262 commands bit position labeled as - is not used. command operation code reference bit 7 6 5 4 3 2 1 0 mode-set c 1 0 - e b m[1:0] ta b l e 7 load-data-pointer c 0 0 p[4:0] ta b l e 8 device-select c1100a[2:0] ta b l e 9 bank-select c 1 1 1 1 0 i o ta b l e 1 0 blink-select c 1 1 1 0 ab bf[1:0] ta b l e 11 table 6. c bit description bit symbol value description 7c continue bit 0 last control byte in the transfer; next byte will be regarded as display data 1 control bytes continue; next byte will be a command too pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 6 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates [1] the possibility to disable the display allows implementation of blinking under external control. [2] the display is disabled by setting all backplane and segment outputs to v lcd . [3] not applicable for static drive mode. 7.1.2 command: load-data-pointer the load-data-pointer command defines the display ram address where the following display data are sent to. 7.1.3 command: device-select the device-select command allows defining the subaddress counter value. 7.1.4 command: bank-select the bank-select command controls where data is written to ram and wh ere it is displayed from. table 7. mode-set command bit description bit symbol value description 7c0, 1see ta b l e 6 6 to 5 - 10 fixed value 4 - - unused 3e display status [1] 0 disabled (blank) [2] 1 enabled 2b lcd bias configuration [3] 0 1 3 bias 1 1 2 bias 1 to 0 m[1:0] lcd drive mode selection 01 static; bp0 10 1:2 multiplex; bp0, bp1 11 1:3 multiplex; bp0, bp1, bp2 00 1:4 multiplex; bp0, bp1, bp2, bp3 table 8. load-data-pointer command bit description see section 7.6.1 . bit symbol value description 7c0, 1see ta b l e 6 6 to 5 - 00 fixed value 4 to 0 p[4:0] 00000 to 11111 5-bit binary value, 0 to 31; transferred to the data pointer to define one of 32 display ram addresses table 9. device-select command bit description see section 7.6.2 . bit symbol value description 7c0, 1see ta b l e 6 6 to 3 - 1100 fixed value 2 to 0 a[2:0] 000 to 111 3-bit binary value, 0 to 7; transferred to the subaddress counter to define one of eight hardware subaddresses pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 7 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates [1] the bank-select command has no effect in 1:3 and 1:4 multiplex drive modes. 7.1.5 command: blink-select the blink-select command allows configuring the blink mode and the blink frequency. [1] normal blinking is assumed when the lcd multiplex drive modes 1:3 or 1:4 are selected. [2] alternate ram bank blinking does not apply in 1:3 and 1:4 multiplex drive modes. table 10. bank-select command bit description see section 7.6.5 . bit symbol value description static 1:2 multiplex [1] 7 c 0, 1 see table 6 6 to 2 - 11110 fixed value 1i input bank selection ; storage of arriving display data 0 ram row 0 ram rows 0 and 1 1 ram row 2 ram rows 2 and 3 0o output bank selection ; retrieval of lcd display data 0 ram row 0 ram rows 0 and 1 1 ram row 2 ram rows 2 and 3 table 11. blink-select command bit description see section 7.1.5.1 . bit symbol value description 7c0, 1see ta b l e 6 6 to 3 - 1110 fixed value 2ab blink mode selection 0 normal blinking [1] 1 alternate ram bank blinking [2] 1 to 0 bf[1:0] blink frequency selection 00 off 01 1 10 2 11 3 pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 8 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates 7.1.5.1 blinking the display blinking capabilitie s of the pca85262 are very versatile. the whole display can blink at frequencie s selected by the blink-select command (see table 11 ). the blink frequencies are derived from the clock freque ncy. the ratio between the clock and blink frequencies depends on the blink mode selected (see ta b l e 1 2 ). an additional feature is for an arbitrary select ion of lcd elements to blink. this applies to the static and 1:2 multiplex drive modes and can be implemented without any communication overheads. with the output bank selector, the displayed ram banks are exchanged with alternate ram banks at the blink frequency. this mode can also be specified by the b link-select command. in the 1:3 and 1:4 multiplex modes, where no al ternative ram bank is available, groups of lcd elements can blink by selectively changing the display ram data at fixed time intervals. the entire display can blink at a frequency other than the nominal blink frequency. this can be effectively performed by resetting and setting the display enable bit e at the required rate using the mode-set command (see ta b l e 7 ). [1] the blink frequency is proporti onal to the clock frequency (f clk ). for the range of the clock frequency, see ta b l e 2 0 . 7.2 initialization at power-on the status of the i 2 c-bus and the registers of the pca85262 is undefined. therefore the pca85262 should be initialized as quickly as possible after power-on to ensure a proper bus communication and to avoid display artifacts. the following instructions should be accomplished for initialization: ? i 2 c-bus (see section 8 ) initialization (only necessary if no communication with another i 2 c device on the bus has already taken place, since that would have reset the i 2 c-interface of the pca85262) ? generating a start condition ? sending 0h (1 byte) and ignoring the acknowledge ? generating a stop condition ? mode-set command (see ta b l e 7 ), setting ? bit e = 0 ? bit b to the required lcd bias configuration table 12. blink frequencies blink mode blink frequency equation [1] off - 1 2 3 f blink f clk 768 --------- - = f blink f clk 1536 ------------ - = f blink f clk 3072 ------------ - = pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 9 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates ? bits m[1:0] to the required lcd drive mode ? load-data-pointer command (see ta b l e 8 ), setting ? bits p[4:0] to 0h (or any other required address) ? device-select command (see ta b l e 9 ), setting ? bits a[2:0] to the required hardware subaddress (for example, 0h) ? bank-select command (see ta b l e 1 0 ), setting ? bit i to 0 ? bit o to 0 ? blink-select command (see ta b l e 11 ), setting ? bit ab to 0 or 1 ? bits bf[1:0] to 00 (or to a desired blinking mode) ? writing meaningful information (for example, a logo) into the display ram after the initialization, the display can be switched on by setting bit e = 1 with the mode-set command. 7.3 possible display configurations the possible display configurations of the pca85262 depend on the number of active backplane outputs required. a selection of display configurations is shown in table 13 . all of these configurations can be implem ented in the typical system shown in figure 4 . fig 3. example of displa ys suitable for pca85262 table 13. selection of possi ble display configurations number of backplanes icons digits/characters dot matrix/ elements 7-segment [1] 14-segment [2] 4 128 16 8 128 dots (4 ? 32) v h j p h q w z l w k g r w v h j p h q w z l w k g r w d q g d f f h q w d d d g r w p d w u l [ pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 10 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates [1] 7 segment display has 8 elements including the decimal point. [2] 14 segment display has 16 elements including decimal point and accent dot. the host microcontroller maintains the 2-line i 2 c-bus communication channel with the pca85262. the internal oscillator is enabled by connecting pin osc to pin v ss . the appropriate biasing voltages for the multiplexed lcd waveforms are generated internally. the only other connections required to complete the system are the power supplies (v dd , v ss , and v lcd ) and the lcd panel chosen for the application. 7.3.1 lcd bias generator fractional lcd biasing voltages are obtained from an internal voltage divider consisting of three impedances connected in series between v lcd and v ss . the center impedance is bypassed by switch if the 1 2 bias voltage level for th e 1:2 multiplex drive mode configuration is selected. the lcd voltage can be temperature compensated externally, using the supply to pin v lcd . 7.3.2 display register the display register holds the display data while the corresponding multiplex signals are generated. 7.3.3 lcd voltage selector the lcd voltage selector coordinates the mult iplexing of the lcd in accordance with the selected lcd drive configuration. the operation of the voltage selector is controlled by the mode-set command from the command decoder. the biasing configurations that apply to the preferred modes of operatio n, together with the biasing characteristics as functions of v lcd and the resulting discrimina tion ratios (d) are given in ta b l e 1 4 . 39 61 269 6 d o t s ( 3 ? 32) 26 4846 4 d o t s ( 2 ? 32) 13 2423 2 d o t s ( 1 ? 32) the resistance of the power lines must be kept to a minimum. fig 4. typical system configuration table 13. selection of possi ble display configurations number of backplanes icons digits/characters dot matrix/ elements 7-segment [1] 14-segment [2] d d d 3 & $ $ $ $ 6 $ + 2 6 7 0 , & 5 2 & 2 1 7 5 2 / / ( 5 9 ' ' 9 6 6 6 ' $ 6 & / 2 6 & 9 ' ' 9 / & ' 9 6 6 v h j p h q w g u l y h v e d f n s o d q h v / & ' 3 $ 1 ( / x s w r h o h p h q w v 5 ? w u & % pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 11 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates discrimination is a term which is defined as the ratio of the on and off rms voltage across a segment. it can be thought of as a measurement of contrast. a practical value for v lcd is determined by equating v off(rms) with a defined lcd threshold voltage (v th(off) ), typically when the lcd exhibits approximately 10 % contrast. in the static drive mode, a suitable choice is v lcd >3v th(off) . multiplex drive modes of 1:3 and 1:4 with 1 2 bias are possible but the discrimination and hence the contrast ratios are smaller. bias is calculated by , where the values for a are a = 1 for 1 2 bias a = 2 for 1 3 bias the rms on-state voltage (v on(rms) ) for the lcd is calculated with equation 1 : (1) where the values for n are n = 1 for static drive mode n = 2 for 1:2 multiplex drive mode n = 3 for 1:3 multiplex drive mode n = 4 for 1:4 multiplex drive mode the rms off-state voltage (v off(rms) ) for the lcd is calculated with equation 2 : (2) discrimination is the ratio of v on(rms) to v off(rms) and is determined from equation 3 : (3) table 14. biasing characteristics lcd drive mode number of: lcd bias configuration backplanes levels static 1 2 static 0 1 ? 1:2 multiplex 2 3 1 2 0.354 0.791 2.236 1:2 multiplex 2 4 1 3 0.333 0.745 2.236 1:3 multiplex 3 4 1 3 0.333 0.638 1.915 1:4 multiplex 4 4 1 3 0.333 0.577 1.732 v off rms ?? ------------------------ - v on rms ?? ----------------------- - d v on rms ?? off rms ?? ------------------------ - = 1 1a + ------------ - v on rms ?? a 2 2a n ++ n 1a + ?? ? ----------------------------- - v lcd = v off rms ?? a 2 2a ? n + n 1a + ?? ? ----------------------------- - v lcd = d v on rms ?? off rms ?? ---------------------- - a 2 2a n ++ a 2 2a ? n + --------------------------- == pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 12 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates using equation 3 , the discrimination for an lcd drive mode of 1:3 multiplex with 1 2 bias is and the discrimination for an lcd drive mode of 1:4 multiplex with 1 2 bias is . the advantage of these lcd drive modes is a reduction of the lcd full scale voltage v lcd as follows: ? 1:3 multiplex ( 1 2 bias): ? 1:4 multiplex ( 1 2 bias): these compare with when 1 3 bias is used. v lcd is sometimes referred as the lcd operating voltage. 7.3.3.1 electro-optical performance suitable values for v on(rms) and v off(rms) are dependent on the lcd liquid used. the rms voltage, at which a pixel will be switched on or off, determine the transmissibility of the pixel. for any given liquid, there are two threshold values defined. one point is at 10 % relative transmission (at v th(off) ) and the other at 90 % relative transmission (at v th(on) ), see figure 5 . for a good contrast performance, the following rules should be followed: (4) (5) v on(rms) and v off(rms) are properties of the display driver and are affected by the selection of a, n (see equation 1 to equation 3 ) and the v lcd voltage. v th(off) and v th(on) are properties of the lcd liquid and can be provided by the module manufacturer. v th(off) is sometimes just named v th . v th(on) is sometimes named saturation voltage v sat . it is important to match the module properties to those of the driver in order to achieve optimum performance. 3 1.732 = 21 3 ---------- 1.528 = v lcd 6v off rms ?? ? off rms ?? ? ?? --------------------- - 2.309v off rms ?? off rms ?? v on rms ?? v th on ?? ? v off rms ?? v th off ?? ? pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 13 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates fig 5. electro-optical characteristic: relative transmission curve of the liquid 9 5 0 6 > 9 @ 2 ) ) 6 ( * 0 ( 1 7 * 5 ( < 6 ( * 0 ( 1 7 2 1 6 ( * 0 ( 1 7 9 w k r i i 9 w k r q 5 h o d w l y h 7 u d q v p l v v l r q d d d pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 14 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates 7.3.4 lcd drive mode waveforms 7.3.4.1 static drive mode the static lcd drive mode is used when a single backplane is provided in the lcd. the backplane (bpn) and segment (sn) drive waveforms for this mode are shown in figure 6 . v state1 (t) = v sn (t) ? v bp0 (t). v on(rms) = v lcd . v state2 (t) = v (sn + 1) (t) ? v bp0 (t). v off(rms) = 0 v. fig 6. static driv e mode waveforms d d d 9 6 6 9 / & ' 9 6 6 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' v w d w h 9 % 3 6 q 6 q v w d w h 9 d : d y h i r u p v d w g u l y h u e 5 h v x o w d q w z d y h i r u p v d w / & ' v h j p h q w / & ' v h j p h q w v v w d w h r q v w d w h r i i 7 i u pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 15 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates 7.3.4.2 1:2 multiplex drive mode when two backplanes are provided in the lcd, the 1:2 multiplex mode applies. the pca85262 allows the use of 1 2 bias or 1 3 bias in this mode as shown in figure 7 and figure 8 . v state1 (t) = v sn (t) ? v bp0 (t). v on(rms) = 0.791v lcd . v state2 (t) = v sn (t) ? v bp1 (t). v off(rms) = 0.354v lcd . fig 7. waveforms for the 1:2 multiplex drive mode with 1 2 bias d d d v w d w h % 3 d : d y h i r u p v d w g u l y h u e 5 h v x o w d q w z d y h i r u p v d w / & ' v h j p h q w / & ' v h j p h q w v v w d w h % 3 v w d w h v w d w h 9 6 6 9 / & ' 9 / & ' 9 6 6 9 6 6 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 9 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 6 q 6 q 7 i u pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 16 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates v state1 (t) = v sn (t) ? v bp0 (t). v on(rms) = 0.745v lcd . v state2 (t) = v sn (t) ? v bp1 (t). v off(rms) = 0.333v lcd . fig 8. waveforms for the 1:2 multiplex drive mode with 1 3 bias d d d v w d w h % 3 d : d y h i r u p v d w g u l y h u e 5 h v x o w d q w z d y h i r u p v d w / & ' v h j p h q w / & ' v h j p h q w v v w d w h % 3 v w d w h v w d w h 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 6 q 6 q 7 i u 9 6 6 9 / & ' 9 / & ' 9 / & ' pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 17 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates 7.3.4.3 1:3 multiplex drive mode when three backplanes are provided in the lcd, the 1:3 multiplex drive mode applies, as shown in figure 9 . v state1 (t) = v sn (t) ? v bp0 (t). v on(rms) = 0.638v lcd . v state2 (t) = v sn (t) ? v bp1 (t). v off(rms) = 0.333v lcd . fig 9. waveforms for the 1:3 multiplex drive mode with 1 3 bias d d d v w d w h % 3 e 5 h v x o w d q w z d y h i r u p v d w / & ' v h j p h q w / & ' v h j p h q w v v w d w h % 3 v w d w h v w d w h d : d y h i r u p v d w g u l y h u % 3 6 q 6 q 6 q 7 i u 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 18 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates 7.3.4.4 1:4 multiplex drive mode when four backplanes are provided in the lcd, the 1:4 multiplex drive mode applies as shown in figure 10 . v state1 (t) = v sn (t) ? v bp0 (t). v on(rms) = 0.577v lcd . v state2 (t) = v sn (t) ? v bp1 (t). v off(rms) = 0.333v lcd . fig 10. waveforms for the 1:4 multiplex drive mode with 1 3 bias d d d v w d w h % 3 e 5 h v x o w d q w z d y h i r u p v d w / & ' v h j p h q w / & ' v h j p h q w v v w d w h % 3 v w d w h v w d w h % 3 d : d y h i r u p v d w g u l y h u % 3 6 q 6 q 6 q 6 q 7 i u 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' 9 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 / & ' 9 6 6 9 / & ' 9 / & ' 9 / & ' pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 19 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates 7.4 oscillator 7.4.1 internal clock the internal logic of the pca85262 and its lcd drive signals are timed either by its internal oscillator or by an external clock. the internal osc illator is enabled by connecting pin osc to pin v ss . if the internal oscillator is used, the output from pin clk can be used as the clock signal for several pca85262 in the system that are connected in cascade. 7.4.2 external clock pin clk is enabled as an external clock input by connecting pin osc to v dd . the lcd frame frequency is determined by the clock frequency (f clk ). remark: a clock signal must always be supplied to the device; removing the clock may freeze the lcd in a dc state, which is not suitable for the liquid crystal. 7.4.3 timing the pca85262 timing controls the internal da ta flow of the device. this includes the transfer of display data from the display ram to the display segment outputs. in cascaded applications, the correct timing relationship between each pca85262 in the system is maintained by the synchronization signal at pin sync . the timing also generates the lcd frame frequency signal. the frame frequency signal is a fixed division of the clock frequency from either the internal or an external clock: 7.5 backplane and segment outputs 7.5.1 backplane outputs the lcd drive section includes four backplane outputs bp0 to bp3 which must be connected directly to the lcd. the backplane output signals are generated in accordance with the selected lcd drive mode. if less than four backplane outputs are required, the unused outputs can be left open-circuit. ? in 1:3 multiplex drive mode, bp3 carries the same signal as bp1, therefore these two adjacent outputs can be tied togethe r to give enhanced drive capabilities ? in 1:2 multiplex drive mode, bp0 and bp2, respectively, bp1 and bp3 carry the same signals and may also be paired to increase the drive capabilities ? in static drive mode, the same signal is ca rried by all four backplane outputs and they can be connected in parallel for very high drive requirements 7.5.2 segment outputs the lcd drive section includes 32 segment outputs (s0 to s31) which should be connected directly to the lcd. the segment output signals are generated in accordance with the multiplexed backplane signals and with data residing in the display register. when less than 32 segment outputs are required, the unused segment outputs should be left open-circuit. 7.6 display ram the display ram is a static 32 ? 4-bit ram which stores lcd data. f fr f clk 24 ------- = pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 20 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates there is a one-to-one correspondence between ? the bits in the ram bitmap and the lcd elements ? the ram columns and the segment outputs ? the ram rows and the backplane outputs. a logic 1 in the ram bitmap indicates the on-state of the corresponding lcd element; similarly, a logic 0 indicates the off-state. the display ram bitmap, figure 11 , shows the rows 0 to 3 which correspond with the backplane outputs bp0 to bp3, and the columns 0 to 31 which correspond with the segment outputs s0 to s31. in multiplexed lcd applications the segment data of the first, second, third, and fourth row of the display ram are time-multiplexed with bp0, bp1, bp2, and bp3 respectively. when display data is transmitted to the pca8 5262, the display bytes received are stored in the display ram in accordance with the se lected lcd drive mode. the data is stored as it arrives and depending on the current multiplex drive mode the bits are stored singularly, in pairs, triples or quadrupl es. to illustrate the filling order, an example of a 7-segment numeric display showing all drive modes is given in figure 12 ; the ram filling organization depicted applies equally to other lcd types. ? in static drive mode the eight transmitted data bits are placed into row 0 as one byte ? in 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into row 0 and 1 as four succes sive 2-bit ram words ? in 1:3 multiplex drive mode the eight bits are placed in triples into row 0, 1, and 2 as three successive 3-bit ram words, with bit 3 of the third address left unchanged. it is not recommended to use this bit in a displa y because of the difficult addressing. this last bit may, if necessary, be controlled by an additional transfer to this address, but care should be taken to avoid overwriting adjacent data because always full bytes are transmitted (see section 7.6.4 ) ? in 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples into row 0, 1, 2, and 3 as two successive 4-bit ram words the display ram bitmap shows the direct relationship between the display ram column and the segment outputs; and between the bits in a ram row and the backplane outputs. fig 11. display ram bitmap g l v s o d \ 5 $ 0 d g g u h v v h v v h j p h q w r x w s x w v 6 f r o x p q v g l v s o d \ 5 $ 0 u r z v e d f n s o d q h r x w s x w v % 3 u r z v d d f xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 21 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driver for low multiplex rates x = data bit unchanged. fig 12. relationship between lcd layout, drive mode, display ram filling order, and display data transmitted over the i 2 c-bus d d m d f e ' 3 i h j g 0 6 % / 6 % e ' 3 f d g j i h 0 6 % / 6 % d e i j h f g ' 3 0 6 % / 6 % f e d i j h g ' 3 0 6 % / 6 % g u l y h p r g h v w d w l f p x o w l s o h [ p x o w l s o h [ p x o w l s o h [ / & ' v h j p h q w v / & ' e d f n s o d q h v g l v s o d \ 5 $ 0 i l o o l q j r u g h u w u d q v p l w w h g g l v s o d \ e \ w h % 3 % 3 % 3 % 3 % 3 % 3 % 3 % 3 % 3 % 3 q f [ [ [ e [ [ [ d [ [ [ i [ [ [ j [ [ [ h [ [ [ g [ [ [ ' 3 [ [ [ q q q q q q q u r z v g l v s o d \ 5 $ 0 u r z v e d f n s o d q h r x w s x w v % 3 e \ w h f r o x p q v g l v s o d \ 5 $ 0 d g g u h v v v h j p h q w r x w s x w v v q d e [ [ i j [ [ h f [ [ g ' 3 [ [ q q q e \ w h e \ w h u r z v g l v s o d \ 5 $ 0 u r z v e d f n s o d q h r x w s x w v % 3 f r o x p q v g l v s o d \ 5 $ 0 d g g u h v v v h j p h q w r x w s x w v v q e ' 3 f [ d g j [ i h [ [ q q e \ w h e \ w h e \ w h u r z v g l v s o d \ 5 $ 0 u r z v e d f n s o d q h r x w s x w v % 3 f r o x p q v g l v s o d \ 5 $ 0 d g g u h v v v h j p h q w r x w s x w v v q q d f e ' 3 i h j g e \ w h e \ w h e \ w h e \ w h e \ w h u r z v g l v s o d \ 5 $ 0 u r z v e d f n s o d q h r x w s x w v % 3 f r o x p q v g l v s o d \ 5 $ 0 d g g u h v v v h j p h q w r x w s x w v v 6 q 6 q 6 q 6 q ' 3 d i e j h f g 6 q 6 q 6 q 6 q 6 q 6 q 6 q 6 q ' 3 d i e j h f g 6 q 6 q 6 q ' 3 d i e j h f g 6 q 6 q ' 3 d i e j h f g pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 22 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates 7.6.1 data pointer the addressing mechanism for the display ram is realized using the data pointer. this allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display ram. the sequen ce commences with the initialization of the data pointer by the load-data-pointer command (see ta b l e 8 ). following this command, an arriving data byte is stored at the display ram address indicated by the data pointer. the filling order is shown in figure 12 . after each byte is stored, the content of the da ta pointer is automatically incremented by a value dependent on the selected lcd drive mode: ? in static drive mode by eight ? in 1:2 multiplex drive mode by four ? in 1:3 multiplex drive mode by three ? in 1:4 multiplex drive mode by two if an i 2 c-bus data access terminates early, then the state of the data pointer is unknown. consequently, the data pointer must be rewritten prior to further ram accesses. 7.6.2 subaddress counter the storage of display data is determined by the contents of the subaddress counter. storage is allowed only when the content of the subaddress counter matches with the hardware subaddress applied to a0, a1, and a2. the subaddress counter value is defined by the device-select command (see ta b l e 9 ). if the content of the subaddress counter and the hardware subaddress do not match, then data storage is inhibited but the data pointer is incremented as if data storage had take n place. the subaddress counter is also incremented when the data pointer overflows. 7.6.3 ram addressing in cascaded applications in cascaded applications each pca85262 in the cascade must be addressed separately. initially, the first pca85262 is selected by sending the device-select command matching the first device's hardware subaddress. then the data pointer is set to the preferred display ram address by sending the load-data-pointer command. once the display ram of the first pca85262 has been written, the second pca85262 is selected by sending the device-select comma nd again. this time however the command matches the second device's hardware subaddress. next the load-data-pointer command is sent to select the preferred disp lay ram address of the second pca85262. this last step is very important because duri ng writing data to the first pca85262, the data pointer of the second pca85262 is incremented. in addition, the hardware subaddress should not be changed while the device is being accessed on the i 2 c-bus interface. 7.6.4 ram writing in 1:3 multiplex drive mode in 1:3 multiplex drive mode, t he ram is written as shown in ta b l e 1 5 (see figure 12 as well). pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 23 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates if the bit at position bp2/s2 would be writ ten by a second byte tr ansmitted, then the mapping of the segment bits would cha nge as illustrated in ta b l e 1 6 . in the case described in ta b l e 1 6 the ram has to be written entirely and bp2/s2, bp2/s5, bp2/s8 etc. have to be connected to elements on the display. this can be achieved by a combination of writing and re writing the ram like follows: ? in the first write to the ram, bits a7 to a0 are written ? the data-pointer (see section 7.6.1 on page 22 ) has to be set to the address of bit a1 ? in the second write, bits b7 to b0 are writt en, overwriting bits a1 and a0 with bits b7 and b6 ? the data-pointer has to be set to the address of bit b1 ? in the third write, bits c7 to c0 are writte n, overwriting bits b1 and b0 with bits c7 and c6 depending on the method of wr iting to the ram (standard or entire filling by rewriting), some elements remain unused or can be used, but it has to be considered in the module layout process as well as in the driver software design. 7.6.5 bank selection 7.6.5.1 output bank selector the output bank selector (see ta b l e 1 0 ) selects one of the four rows per display ram address for transfer to the display register. the actual row selected depends on the particular lcd drive mode in operation and on the instant in the multiplex sequence. ? in 1:4 multiplex mode, all ram addresses of row 0 are selected, these are followed by the contents of row 1, 2, and then 3 ? in 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially table 15. standard ram filling in 1:3 multiplex drive mode assumption: bp2/s2, bp2/s5, bp2/s8 etc. are not connected to any elements on the display. display ram bits (rows)/ backplane outputs (bpn) display ram addresses (columns)/segment outputs (sn) 0 1 2 3 4 5 6 7 8 9 : 0 a7 a4 a1 b7 b4 b1 c7 c4 c1 d7 : 1 a6 a3 a0 b6 b3 b0 c6 c3 c0 d6 : 2 a5 a2 - b5 b2 - c5 c2 - d5 : 3 ----------: table 16. entire ram filling by rewriting in 1:3 multiplex drive mode assumption: bp2/s2, bp2/s5, bp2/s8 etc. are connected to elements on the display. display ram bits (rows)/ backplane outputs (bpn) display ram addresses (columns)/segment outputs (sn) 0 1 2 3 4 5 6 7 8 9 : 0 a7 a4 a1/b7 b4 b1/c7 c4 c1/d7 d4 d1/e7 e4 : 1 a6 a3 a0/b6 b3 b0/c6 c3 c0/d6 d3 d0/e6 e3 : 2 a5 a2 b5 b2 c5 c2 d5 d2 e5 e2 : 3 ----------: pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 24 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates ? in 1:2 multiplex mode, rows 0 and 1 are selected ? in static mode, row 0 is selected 7.6.5.2 input bank selector the input bank selector loads display data into the display ram in accordance with the selected lcd drive configuration. display data can be loaded in row 2 in static drive mode or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command (see ta b l e 1 0 ). the input bank selector functions inde pendently to the output bank selector. 7.6.5.3 ram bank switching the pca85262 includes a ram bank switching feature in the static and 1:2 multiplex drive modes. a bank can be thought of as one ram row or a collection of ram rows (see figure 13 ). the ram bank switching gives the prov ision for preparing display information in an alternative bank and to be able to switch to it once it is complete. there are two banks; bank 0 and bank 1. figure 13 shows the location of these banks relative to the ram map. input and output banks can be set independently from one another with the bank-select command (see table 10 on page 7 ). figure 14 shows the concept. fig 13. ram banks in static and multiplex driving mode 1:2 g l v s o d \ 5 $ 0 d g g u h v v h v f r o x p q v v h j p h q w r x w s x w v 6 g l v s o d \ 5 $ 0 e l w v u r z v e d f n s o d q h r x w s x w v % 3 d d d e d q n e d q n e d q n e d q n 6 w d w l f g u l y h p r g h 0 x o w l s o h [ g u l y h p r g h pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 25 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates in the static drive mode, the bank-select co mmand may request the contents of row 2 to be selected for display instead of the contents of row 0. in the 1:2 multiplex mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. this gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is assembled. in figure 15 an example is shown for 1:2 multiplex drive mode where the displayed data is read from the first two rows of the memory (bank 0), while the transmitted data is stored in the second two rows of the memory (bank 1). fig 14. bank selection fig 15. example of the bank-select comm and with multiplex drive mode 1:2 0 , & 5 2 & 2 1 7 5 2 / / ( 5 ' , 6 3 / $ < 5 $ 0 % $ 1 . % $ 1 . d d d l q s x w e d q n v h o h f w l r q f r q w u r o v w k h l q s x w g d w d s d w k r x w s x w e d q n v h o h f w l r q f r q w u r o v w k h r x w s x w g d w d s d w k g l v s o d \ 5 $ 0 f r o x p q v v h j p h q w r x w s x w v 6 f r o x p q v g l v s o d \ 5 $ 0 u r z v e d f n s o d q h r x w s x w v % 3 u r z v d d d w r w k h / & ' r x w s x w 5 $ 0 e d q n l q s x w 5 $ 0 e d q n w r w k h 5 $ 0 pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 26 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates 8. characteristics of the i 2 c-bus the i 2 c-bus is for bidirectional, two-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. 8.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see figure 16 ). 8.2 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line while the clock is high is defined as the start condition - s. a low-to-high transition of the data line while the clock is high is defined as the stop condition - p. the start and stop condit ions are illustrated in figure 17 . 8.3 system configuration a device generating a message is a transmitter, a device receiving a message is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves. the system configuration is shown in figure 18 . fig 16. bit transfer p e d g d w d o l q h v w d e o h g d w d y d o l g f k d q j h r i g d w d d o o r z h g 6 ' $ 6 & / fig 17. definition of start and stop conditions p e f 6 ' $ 6 & / 3 6 7 2 3 f r q g l w l r q 6 ' $ 6 & / 6 6 7 $ 5 7 f r q g l w l r q pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 27 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates 8.4 acknowledge the number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlim ited. each byte of eight bits is followed by an acknowledge cycle. ? a slave receiver, which is addressed, must generate an acknowledge after the reception of each byte ? a master receiver must generate an acknowle dge after the reception of each byte that has been clocked out of the slave transmitter ? the device that acknowledges must pull-down the sda line during the acknowledge clock pulse, so that the sda line is st able low during the high period of the acknowledge related clock pulse (set-up and hold times must be considered) ? a master receiver must signal an end of da ta to the transmitter by not generating an acknowledge on the last byte that has been cl ocked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition acknowledgement on the i 2 c-bus is illustrated in figure 19 . fig 18. system configuration p j d 6 ' $ 6 & / 0 $ 6 7 ( 5 7 5 $ 1 6 0 , 7 7 ( 5 5 ( & ( , 9 ( 5 0 $ 6 7 ( 5 7 5 $ 1 6 0 , 7 7 ( 5 6 / $ 9 ( 7 5 $ 1 6 0 , 7 7 ( 5 5 ( & ( , 9 ( 5 6 / $ 9 ( 5 ( & ( , 9 ( 5 0 $ 6 7 ( 5 7 5 $ 1 6 0 , 7 7 ( 5 5 ( & ( , 9 ( 5 fig 19. acknowledgement of the i 2 c-bus p e f 6 6 7 $ 5 7 f r q g l w l r q f o r f n s x o v h i r u d f n q r z o h g j h p h q w q r w d f n q r z o h g j h d f n q r z o h g j h g d w d r x w s x w e \ w u d q v p l w w h u g d w d r x w s x w e \ u h f h l y h u 6 & / i u r p p d v w h u pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 28 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates 8.5 i 2 c-bus controller the pca85262 acts as an i 2 c-bus slave receiver. it does not initiate i 2 c-bus transfers or transmit data to an i 2 c-bus master receiver. the only data output from the pca85262 are the acknowledge signals of the selected devices. device selection depends on the i 2 c-bus slave address, on the transferre d command data and on the hardware subaddress. in single device applications, the hardw are subaddress inputs a0, a1, and a2 are normally tied to v ss which defines the hardware subaddress 0. in multiple device applications a0, a1, and a2 are tied to v ss or v dd using a binary coding scheme, so that no two devices with a common i 2 c-bus slave address have the same hardware subaddress. 8.6 input filters to enhance noise immunity in electrically ad verse environments, rc low-pass filters are provided on the sda and scl lines. 8.7 i 2 c-bus protocol two i 2 c-bus slave addresses (0111 000 and 0111 001) are used to address the pca85262. the entire i 2 c-bus slave address byte is shown in table 17 . the pca85262 is a write-only device and will not resp ond to a read acce ss, therefore bit 0 should always be logic 0. bit 1 of the slave address byte that a pca8 5262 responds to, is defined by the level tied to its sa0 input (v ss for logic 0 and v dd for logic 1). having two reserved slave addresses allows the following on the same i 2 c-bus: ? up to 16 pca85262 for very large lcd applications ? the use of two types of lcd multiplex drive modes the i 2 c-bus protocol is shown in figure 20 . the sequence is initiated with a start condition (s) from the i 2 c-bus master which is followed by one of the two possible pca85262 slave addresses available. all pca85262 whose sa0 inputs correspond to bit 0 of the slave address respond by asse rting an acknowledge in parallel. this i 2 c-bus transfer is ignored by all pca85262 whose sa0 inputs are set to the alternative level. table 17. i 2 c slave address byte slave address bit 7 6 5 4 3 2 1 0 msb lsb 011100sa0r/w pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 29 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates after an acknowledgement, one or more command bytes follow that define the status of each addressed pca85262. the last command byte sent is identified by resetting its most signif icant bit, continuation bit c (see figure 21 ). the command bytes are also acknowledged by all addressed pca85262 on the bus. after the last command byte, one or more display data bytes may follow. display data bytes are stored in the display ram at the address specified by the data pointer and the subaddress counter. both data pointer and subaddress counter are automatically updated and the data directed to the intended pca85262 device. an acknowledgement after each byte is asserted only by the pca85262 that are addressed via address lines a0, a1, and a2. after the last display byte, the i 2 c-bus master asserts a stop condition (p). alternately a start may be asserted to restart an i 2 c-bus access. fig 20. i 2 c-bus protocol fig 21. format of command byte d d d 6 $ 6 $ & & 2 0 0 $ 1 ' $ 3 $ ' , 6 3 / $ < ' $ 7 $ v o d y h d g g u h v v 5 : d f n q r z o h g j h e \ d o o d g g u h v v h g 3 & $ d f n q r z o h g j h e \ $ $ d q g $ v h o h f w h g 3 & $ r q o \ e \ w h x s g d w h g d w d s r l q w h u v d q g l i q h f h v v d u \ v x e d g g u h v v f r x q w h u q ? e \ w h v q ? e \ w h v p v d 5 ( 6 7 2 ) 2 3 & 2 ' ( & 0 6 % / 6 % pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 30 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates 9. internal circuitry fig 22. device protection circuits 6 $ 9 ' ' 9 ' ' 9 6 6 9 6 6 9 / & ' 9 6 6 6 ' $ d d f 9 6 6 6 & / 9 6 6 & / . 9 ' ' 9 6 6 2 6 & 9 ' ' 9 6 6 6 < 1 & 9 ' ' 9 6 6 $ $ $ 9 ' ' 9 6 6 % 3 % 3 % 3 % 3 9 / & ' 9 6 6 6 w r 6 9 / & ' 9 6 6 pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 31 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates 10. safety notes 11. limiting values [1] pass level; human body model (hbm), according to ref. 8 ? jesd22-a114 ? . [2] pass level; charged-device model (cdm), according to ref. 9 ? jesd22-c101 ? . [3] pass level; latch-up testing according to ref. 10 ? jesd78 ? at maximum ambient temperature (t amb(max) ). [4] according to the store and transport requirements (see ref. 14 ? um10569 ? ) the devices have to be stored at a temperature of +8 ? c to +45 ? c and a humidity of 25 % to 75 %. caution this device is sensitive to electrostatic di scharge (esd). observe precautions for handling electrostatic sensitive devices. such precautions are described in the ansi/esd s20.20 , iec/st 61340-5 , jesd625-a or equivalent standards. caution static voltages across the liquid crystal display can build up when the lcd supply voltage (v lcd ) is on while the ic supply voltage (v dd ) is off, or vice versa. this may cause unwanted display artifacts. to av oid such artifacts, v lcd and v dd must be applied or removed together. table 18. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage ? 0.5 +6.5 v v lcd lcd supply voltage ? 0.5 +9.0 v v i input voltage on each of the pins clk, sda, scl, sync , sa0, osc, a0 to a2 ? 0.5 +6.5 v v o output voltage on each of the pins s0 to s31, bp0 to bp3 ? 0.5 +9.0 v i i input current ? 10 +10 ma i o output current ? 10 +10 ma i dd supply current ? 50 +50 ma i dd(lcd) lcd supply current ? 50 +50 ma i ss ground supply current ? 50 +50 ma p tot total power dissipation - 400 mw p o output power - 100 mw v esd electrostatic discharge voltage hbm [1] - ? 5000 v cdm [2] - ? 1500 v i lu latch-up current v lu =11.5v [3] - 200 ma t stg storage temperature [4] ? 65 +150 ? c t amb ambient temperature operating device ? 40 +105 ? c pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 32 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates 12. static characteristics table 19. static characteristics v dd = 1.8 v to 5.5 v; v ss = 0 v; v lcd = 2.5 v to 8.0 v; t amb = ? 40 ? c to +105 ? c; unless otherwise specified. symbol parameter conditions min typ max unit supplies v dd supply voltage v lcd ? 6.5 v 1.8 - 5.5 v v lcd > 6.5 v 2.5 - 5.5 v v lcd lcd supply voltage v dd < 2.5 v 2.5 - 6.5 v v dd ? 2.5 v 2.5 - 8.0 v i dd supply current f clk(ext) = 1536 hz [1] [2] -620 ? a v dd =3.0v; t amb =25 ?c -2.7- ? a i dd(lcd) lcd supply current f clk(ext) = 1536 hz [1] -1832 ? a v lcd =3.0v; t amb =25 ?c - 17.5 - ? a logic [3] v il low-level input voltage on pins clk, sync , osc, a0 to a2, sa0, scl, sda v ss -0.3v dd v v ih high-level input voltage on pins clk, sync , osc, a0 to a2, sa0, scl, sda [4] [5] 0.7v dd -v dd v i ol low-level output current output sink current; v ol = 0.4 v; v dd =5v on pins clk and sync 1- - ma on pin sda 3 - - ma i oh(clk) high-level output current on pi n clk output source current; v oh =4.6v; v dd =5v 1- - ma i l leakage current v i =v dd or v ss ; on pins clk, scl, sda, a0 to a2, and sa0 ? 1- +1 ? a i l(osc) leakage current on pin osc v i =v dd ? 1- +1 ? a c i input capacitance [6] --7pf pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 33 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates [1] lcd outputs are open-circuit; inputs at v ss or v dd ; external clock with 50 % duty factor; i 2 c-bus inactive. [2] for typical values, see figure 23 . [3] the i 2 c-bus interface of pca85262 is 5 v tolerant. [4] when tested, i 2 c pins scl and sda have no diode to v dd and may be driven to the v i limiting values given in ta b l e 1 8 (see figure 22 as well). [5] propagation delay of driver between clock (clk) and lcd driving signals. [6] periodically sampled, not 100 % tested. [7] outputs measured one at a time. lcd outputs ? v o output voltage variation on pins bp0 to bp3 and s0 to s31 ? 100 - +100 mv r o output resistance v lcd = 5 v [7] on pins bp0 to bp3 - 1.5 - k ? on pins s0 to s31 - 6.0 - k ? table 19. static characteristics ?continued v dd = 1.8 v to 5.5 v; v ss = 0 v; v lcd = 2.5 v to 8.0 v; t amb = ? 40 ? c to +105 ? c; unless otherwise specified. symbol parameter conditions min typ max unit t amb =30 ? c; 1:4 multiplex drive mode; v lcd = 6.5 v; f clk(ext) = 1.536 khz; all ram written with logic 1; no display connected; i 2 c-bus inactive. fig 23. typical i dd with respect to v dd 9 ' ' 9 d d o , ' ' ? $ pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 34 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates 13. dynamic characteristics [1] typical output duty factor: 50 % measured at the clk output pin. [2] not tested in production. [3] all timing values are valid within the operating supply voltage and ambient temperature range and are referenced to v il and v ih with an input voltage swing of v ss to v dd . table 20. dynamic characteristics v dd = 1.8 v to 5.5 v; v ss = 0 v; v lcd = 2.5 v to 8.0 v; t amb = ? 40 ? c to +105 ? c; unless otherwise specified. symbol parameter conditions min typ max unit clock f clk(int) internal clock frequency [1] 3505 4800 6240 hz f clk(ext) external clock frequency 960 - 6720 hz f fr frame frequency internal clock 146 200 260 hz external clock 40 - 280 hz t clk(h) high-level clock time 60 - - ? s t clk(l) low-level clock time 60 - - ? s synchronization t pd(sync_n) sync propagation delay - 30 - ns t sync_nl sync low time 1 - - ? s t pd(drv) driver propagation delay v lcd = 5 v [2] --3 0 ? s i 2 c-bus [3] pin scl f scl scl clock frequency - - 400 khz t low low period of the scl clock 1.3 - - ? s t high high period of the scl clock 0.6 - - ? s pin sda t su;dat data set-up time 100 - - ns t hd;dat data hold time 0 - - ns pins scl and sda t buf bus free time between a stop and start condition 1.3 - - ? s t su;sto set-up time for stop condition 0.6 - - ? s t hd;sta hold time (repeated) start condition 0.6 - - ? s t su;sta set-up time for a repeated start condition 0.6 - - ? s t r rise time of both sda and scl signals f scl = 400 khz - - 0.3 ? s f scl < 125 khz - - 1.0 ? s t f fall time of both sda and scl signals - - 0.3 ? s c b capacitive load for each bus line - - 400 pf t w(spike) spike pulse width on the i 2 c - b u s--5 0n s pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 35 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates 14. application information 14.1 cascaded operation large display configurations of up to 16 pca85262 can be recognized on the same i 2 c-bus by using the 3-bit hardware subaddress (a0, a1, and a2) and the programmable i 2 c-bus slave address (sa0). fig 24. driver timing waveforms fig 25. i 2 c-bus timing waveforms d d d w 3 ' g u y w 6 < 1 & b 1 / w 3 ' 6 < 1 & b 1 & / . 6 < 1 & % 3 q 6 q w f o n + w f o n / i f o n 9 ' ' 9 ' ' 9 ' ' 9 ' ' 6 ' $ p j d 6 ' $ 6 & / w 6 8 6 7 $ w 6 8 6 7 2 w + ' 6 7 $ w % 8 ) w / 2 : w + ' ' $ 7 w + , * + w u w i w 6 8 ' $ 7 pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 36 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates when cascaded pca85262 are synchronized, they can share the backplane signals from one of the devices in the cascade. such an arrangement is cost-effective in large lcd applications since the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display. the other pca85262 of the cascade contribute additional segment outputs. the backplanes c an either be connected together to enhance the drive capability or some can be left open-circuit (such as the ones from the slave in figure 26 ) or just some of the mast er and some of the slave c an be taken to facilitate the layout of the display. table 21. addressing cascaded pca85262 cluster bit sa0 pin a2 pin a1 pin a0 device 100000 0011 0102 0113 1004 1015 1106 1117 210008 0019 01010 01111 10012 10113 11014 11115 pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 37 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates the sync line is provided to maintain the corr ect synchronization between all cascaded pca85262. synchronization is guaranteed afte r a power-on and initialization. the only time that sync is likely to be needed is if synchronization is accidentally lost (e.g. by noise in adverse electrical environments or by defining a multiplex drive mode when pca85262 with different sa0 levels are cascaded). sync is organized as an input/output pin. the output selection is realized as an open-drain driver with an internal pull-up resistor. a pca85262 asserts the sync line at the onset of its last active backplane signal and monitors the sync line at all other times. if synchronization in the cascade is lost, it is restored by the first pca85262 to assert sync . the timing relationship between the backplane waveforms and the sync signal for the various drive modes of the pca85262 are shown in figure 27 . the pca85262 can always be cascaded with other devices of the same type or conditionally with other devices of the same fa mily. this allows opti mal drive selection for a given number of pixels to display. figure 24 and figure 27 show the timing of the synchronization signals. (1) is master (osc connected to v ss ). (2) is slave (osc connected to v dd ). fig 26. cascaded pca85262 configuration + 2 6 7 0 , & 5 2 & 2 1 7 5 2 / / ( 5 6 ' $ 6 & / & / . 2 6 & 6 < 1 & v h j p h q w g u l y h v e d f n s o d q h v v h j p h q w g u l y h v / & ' 3 $ 1 ( / 3 & $ $ $ $ 6 $ 9 6 6 9 6 6 9 6 6 9 ' ' 9 ' ' 9 / & ' 9 / & ' 9 ' ' 9 / & ' d d d 6 ' $ 6 & / 6 < 1 & & / . 2 6 & % 3 w r % 3 r s h q f l u f x l w $ $ $ 6 $ 3 & $ % 3 w r % 3 5 w u & e ? pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 38 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates only one master but mu ltiple slaves are allowed in a ca scade. all devices in the cascade have to use the same clock whether it is supplied externally or provided by the master. if an external clock source is used, all pca8 5262 in the cascade must be configured such as to receive the clock from that exte rnal source (pin osc connected to v dd ). thereby it must be ensured that the clock tree is designed such that on all pca85262 the clock propagation delay from the clock source to all pca85262 in the cascade is as equal as possible since otherwise synchronization artifacts may occur. in mixed cascading configurations , care has to be taken that the specifications of the individual cascaded devices are always met. fig 27. synchronization of the cascade for the various pca85262 drive modes 7 i u i i u % 3 6 < 1 & % 3 e l d v 6 < 1 & % 3 e l d v d v w d w l f g u l y h p r g h e p x o w l s o h [ g u l y h p r g h f p x o w l s o h [ g u l y h p r g h g p x o w l s o h [ g u l y h p r g h % 3 e l d v 6 < 1 & 6 < 1 & % 3 e l d v p j o pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 39 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates 15. test information 15.1 quality information this product has been qualified in accordance with the automotive electronics council (aec) standard q100 - failure mechanism based stress test qualification for integrated circuits , and is suitable for use in automotive applications. pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 40 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates 16. package outline fig 28. package outline sot362-1 (tssop48) of PCA85262ATT 5 h i h u h q f h v 2 x w o l q h y h u v l r q ( x u r s h d q s u r m h f w l r q , v v x h g d w h , ( & - ( ' ( & - ( , 7 $ 6 2 7 0 2 v r w b s r 8 q l w p p p d [ q r p p l q $ ' l p h q v l r q v p p d u h w k h r u l j l q d o g l p h q v l r q v 1 r w h 3 o d v w l f r u p h w d o s u r w u x v l r q v r i p p p d [ l p x p s h u v l g h d u h q r w l q f o x g h g 3 o d v w l f l q w h u o h d g s u r w u x v l r q v r i p p p d [ l p x p s h u v l g h d u h q r w l q f o x g h g 7 6 6 2 3 s o d v w l f w k l q v k u l q n v p d o o r x w o l q h s d f n d j h o h d g v e r g \ z l g w k p p 6 2 7 $ $ $ e s f ' ? ( h + ( / / s 4 y z \ = ? s l q l q g h [ y $ $ ' / s 4 ( = f / h z \ ; $ + ( e s $ $ g h w d l o ; $ p p v f d o h pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 41 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates 17. handling information all input and output pins are protected ag ainst electrostatic discharge (esd) under normal handling. when handling metal-oxide semiconductor (mos) devices ensure that all normal precautions are taken as described in jesd625-a , iec 61340-5 or equivalent standards. pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 42 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates 18. packing information 18.1 tape and reel information for tape and reel packing information, please see ref. 12 ? sot362-1_118 ? on page 49 . 19. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 19.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 19.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 19.3 wave soldering key characteristics in wave soldering are: pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 43 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities 19.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 29 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 2 2 and 23 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 29 . table 22. snpb eutectic process (from j-std-020d) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 ? 350 < 2.5 235 220 ? 2.5 220 220 table 23. lead-free process (from j-std-020d) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 44 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . 20. footprint information msl: moisture sensitivity level fig 29. temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 45 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates fig 30. footprint information for reflow soldering of sot362-1 (tssop48) of PCA85262ATT ' , 0 ( 1 6 , 2 1 6 l q p p $ \ % \ ' ' * \ + \ 3 & * [ v r w b i u + [ 6 2 7 v r o g h u o d q g r f f x s l h g d u h d ) r r w s u l q w l q i r u p d w l r q i r u u h i o r z v r o g h u l q j r i 7 6 6 2 3 s d f n d j h $ \ % \ * \ & + \ + [ * [ 3 * h q h u l f i r r w s u l q w s d w w h u q 5 h i h u w r w k h s d f n d j h r x w o l q h g u d z l q j i r u d f w x d o o d \ r x w 3 ' ' [ 3 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 46 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driver for low multiplex rates 21. appendix 21.1 lcd segment driver selection table 24. selection of lcd segment drivers type name number of elements at mux v dd (v) v lcd (v) f fr (hz) v lcd (v) charge pump v lcd (v) temperature compensat. t amb ( ?c) interface package aec- q100 1:1 1:2 1:3 1:4 1:6 1:8 1:9 pca8553dtt 40 80 120 160 - - - 1.8 to 5.5 1.8 to 5.5 32 to 256 [1] nn ? 40 to 105 i 2 c / spi tssop56 y pca8546att - - - 176 - - - 1.8 to 5.5 2.5 to 9 60 to 300 [1] nn ? 40 to 95 i 2 c tssop56 y pca8546btt - - - 176 - - - 1.8 to 5.5 2.5 to 9 60 to 300 [1] nn ? 40 to 95 spi tssop56 y pca8547aht 44 88 - 176 - - - 1.8 to 5.5 2.5 to 9 60 to 300 [1] yy ? 40 to 95 i 2 ctqfp64y pca8547bht 44 88 - 176 - - - 1.8 to 5.5 2.5 to 9 60 to 300 [1] yy ? 40 to 95 spi tqfp64 y pcf85134hl 60 120 180 240 - - - 1.8 to 5.5 2.5 to 6.5 82 n n ? 40 to 85 i 2 clqfp80n pca85134h 60 120 180 240 - - - 1.8 to 5.5 2.5 to 8 82 n n ? 40 to 95 i 2 clqfp80y pca85134ahl 60 120 180 240 - - - 1.8 to 5.5 2.5 to 8 82 n n ? 40 to 95 i 2 clqfp80y pca8543ahl 60 120 - 240 - - - 2.5 to 5.5 2.5 to 9 60 to 300 [1] yy ? 40 to 105 i 2 clqfp80y pcf8545att - - - 176 252 320 - 1.8 to 5.5 2.5 to 5.5 60 to 300 [1] nn ? 40 to 85 i 2 c tssop56 n pcf8545btt - - - 176 252 320 - 1.8 to 5.5 2.5 to 5.5 60 to 300 [1] nn ? 40 to 85 spi tssop56 n pcf8536at - - - 176 252 320 - 1.8 to 5.5 2.5 to 9 60 to 300 [1] nn ? 40 to 85 i 2 c tssop56 n pcf8536bt - - - 176 252 320 - 1.8 to 5.5 2.5 to 9 60 to 300 [1] nn ? 40 to 85 spi tssop56 n pca8536at - - - 176 252 320 - 1.8 to 5.5 2.5 to 9 60 to 300 [1] nn ? 40 to 95 i 2 c tssop56 y pca8536bt - - - 176 252 320 - 1.8 to 5.5 2.5 to 9 60 to 300 [1] nn ? 40 to 95 spi tssop56 y pcf8537ah 44 88 - 176 276 352 - 1.8 to 5.5 2.5 to 9 60 to 300 [1] yy ? 40 to 85 i 2 ctqfp64n pcf8537bh 44 88 - 176 276 352 - 1.8 to 5.5 2.5 to 9 60 to 300 [1] yy ? 40 to 85 spi tqfp64 n pca8537ah 44 88 - 176 276 352 - 1.8 to 5.5 2.5 to 9 60 to 300 [1] yy ? 40 to 95 i 2 ctqfp64y pca8537bh 44 88 - 176 276 352 - 1.8 to 5.5 2.5 to 9 60 to 300 [1] yy ? 40 to 95 spi tqfp64 y pca9620h 60 120 - 240 320 480 - 2.5 to 5.5 2.5 to 9 60 to 300 [1] yy ? 40 to 105 i 2 clqfp80y pca9620u 60 120 - 240 320 480 - 2.5 to 5.5 2.5 to 9 60 to 300 [1] yy ? 40 to 105 i 2 c bare die y pcf8552dug 36 72 108 144 - - - 1.8 to 5.5 1.8 to 5.5 32 to 128 [1] nn ? 40 to 85 i 2 c / spi bare die n pca8552dug 36 72 108 144 - - - 1.8 to 5.5 1.8 to 5.5 32 to 256 [1] nn ? 40 to 105 i 2 c / spi bare die y pcf8576du 40 80 120 160 - - - 1.8 to 5.5 2.5 to 6.5 77 n n ? 40 to 85 i 2 c bare die n pcf8576eug 40 80 120 160 - - - 1.8 to 5.5 2.5 to 6.5 77 n n ? 40 to 85 i 2 c bare die n xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 47 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driver for low multiplex rates [1] software programmable. [2] hardware selectable. pca8576fug 40 80 120 160 - - - 1.8 to 5.5 2.5 to 8 200 n n ? 40 to 105 i 2 c bare die y pcf85133u 80 160 240 320 - - - 1.8 to 5.5 2.5 to 6.5 82, 110 [2] nn ? 40 to 85 i 2 c bare die n pca85133u 80 160 240 320 - - - 1.8 to 5.5 2.5 to 8 82, 110 [2] nn ? 40 to 95 i 2 c bare die y pca85233ug 80 160 240 320 - - - 1.8 to 5.5 2.5 to 8 150, 220 [2] nn ? 40 to 105 i 2 c bare die y pcf85132u 160 320 480 640 - - - 1.8 to 5.5 1.8 to 8 60 to 90 [1] nn ? 40 to 85 i 2 c bare die n pca8530dug 102 204 - 408 - - - 2.5 to 5.5 4 to 12 45 to 300 [1] yy ? 40 to 105 i 2 c / spi bare die y pca85132u 160 320 480 640 - - - 1.8 to 5.5 1.8 to 8 60 to 90 [1] nn ? 40 to 95 i 2 c bare die y pca85232u 160 320 480 640 - - - 1.8 to 5.5 1.8 to 8 117 to 176 [1] nn ? 40 to 95 i 2 c bare die y pcf8538ug 102 204 - 408 612 816 918 2.5 to 5.5 4 to 12 45 to 300 [1] yy ? 40 to 85 i 2 c / spi bare die n pca8538ug 102 204 - 408 612 816 918 2.5 to 5.5 4 to 12 45 to 300 [1] yy ? 40 to 105 i 2 c / spi bare die y table 24. selection of lcd segment drivers ?continued type name number of elements at mux v dd (v) v lcd (v) f fr (hz) v lcd (v) charge pump v lcd (v) temperature compensat. t amb ( ?c) interface package aec- q100 1:1 1:2 1:3 1:4 1:6 1:8 1:9 pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 48 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates 22. abbreviations table 25. abbreviations acronym description aec automotive electronics council cmos complementary metal-oxide semiconductor cdm charged device model dc direct current hbm human body model i 2 c inter-integrated circuit ic integrated circuit lcd liquid crystal display lsb least significant bit msb most significant bit msl moisture sensitivity level pcb printed-circuit board ram random access memory rc resistance and capacitance rms root mean square scl serial clock line sda serial data line smd surface-mount device pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 49 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates 23. references [1] an10365 ? surface mount reflow soldering description [2] an10853 ? esd and emc sensitivity of ic [3] an11267 ? emc and system level esd design guidelines for lcd drivers [4] an11494 ? cascading nxp lcd segment drivers [5] iec 60134 ? rating systems for electronic tu bes and valves and analogous semiconductor devices [6] iec 61340-5 ? protection of electronic devices from electrostatic phenomena [7] ipc/jedec j-std-020d ? moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices [8] jesd22-a114 ? electrostatic discharge (esd) sensitivity testing human body model (hbm) [9] jesd22-c101 ? field-induced charged-device model test method for electrostatic-discharge-withstand thresh olds of microelectronic components [10] jesd78 ? ic latch-up test [11] jesd625-a ? requirements for handling elec trostatic-discharge-sensitive (esds) devices [12] sot362-1_118 ? tssop48; reel pack; smd, 13", packing information [13] um10204 ? i 2 c-bus specification and user manual [14] um10569 ? store and transport requirements pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 50 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates 24. revision history table 26. revision history document id release date data sheet status change notice supersedes pca85262 v.1 20140211 product data sheet - - pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 51 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates 25. legal information 25.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 25.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 25.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use in automotive applications ? this nxp semiconductors product has been qualified for use in automotive applications. unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification. pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 52 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any licens e under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 25.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 26. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 53 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates 27. tables table 1. ordering information . . . . . . . . . . . . . . . . . . . . .2 table 2. ordering options . . . . . . . . . . . . . . . . . . . . . . . . .2 table 3. marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2 table 4. pin description of PCA85262ATT (tssop48) . .4 table 5. definition of the pca85262 commands . . . . . . .5 table 6. c bit description . . . . . . . . . . . . . . . . . . . . . . . . .5 table 7. mode-set command bit description . . . . . . . . . .6 table 8. load-data-pointer command bit description . . . .6 table 9. device-select command bit description . . . . . . .6 table 10. bank-select command bit description . . . . . . . .7 table 11. blink-select command bit description . . . . . . . .7 table 12. blink frequencies . . . . . . . . . . . . . . . . . . . . . . . .8 table 13. selection of possible display configurations . . . .9 table 14. biasing characteristics . . . . . . . . . . . . . . . . . . . 11 table 15. standard ram filling in 1:3 multiplex drive mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 table 16. entire ram filling by rewriting in 1:3 multiplex drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 table 17. i 2 c slave address byte . . . . . . . . . . . . . . . . . . .28 table 18. limiting values . . . . . . . . . . . . . . . . . . . . . . . . .31 table 19. static characteristics . . . . . . . . . . . . . . . . . . . .32 table 20. dynamic characteristics . . . . . . . . . . . . . . . . . .34 table 21. addressing cascaded pca85262 . . . . . . . . . .36 table 22. snpb eutectic process (from j-std-020d) . . .43 table 23. lead-free process (from j-std-020d) . . . . . .43 table 24. selection of lcd segment drivers . . . . . . . . . .46 table 25. abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 26. revision history . . . . . . . . . . . . . . . . . . . . . . . .50 pca85262 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 1 ? 11 february 2014 54 of 55 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates 28. figures fig 1. block diagram of pca85262 . . . . . . . . . . . . . . . . .3 fig 2. pinning diagram for PCA85262ATT (tssop48) . .4 fig 3. example of displays suitable for pca85262 . . . . .9 fig 4. typical system configuration . . . . . . . . . . . . . . . .10 fig 5. electro-optical ch aracteristic: relative transmission curve of the liquid . . . . . . . . . . . . . .13 fig 6. static drive mode waveforms . . . . . . . . . . . . . . . .14 fig 7. waveforms for the 1:2 multiplex drive mode with 1 2 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 fig 8. waveforms for the 1:2 multiplex drive mode with 1 3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 fig 9. waveforms for the 1:3 multiplex drive mode with 1 3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 fig 10. waveforms for the 1:4 multiplex drive mode with 1 3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 fig 11. display ram bitmap . . . . . . . . . . . . . . . . . . . . . .20 fig 12. relationship between lcd layout, drive mode, display ram filling order, and display data transmitted over the i 2 c-bus . . . . . . . . . . . . . . . .21 fig 13. ram banks in static and multiplex driving mode 1:2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 fig 14. bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . .25 fig 15. example of the bank-select command with multiplex drive mode 1:2 . . . . . . . . . . . . . . . . . . .25 fig 16. bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 fig 17. definition of start and stop conditions. . . . . .26 fig 18. system configuration . . . . . . . . . . . . . . . . . . . . . .27 fig 19. acknowledgement of the i 2 c-bus . . . . . . . . . . . .27 fig 20. i 2 c-bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . .29 fig 21. format of command byte . . . . . . . . . . . . . . . . . . .29 fig 22. device protection circuits . . . . . . . . . . . . . . . . . . .30 fig 23. typical i dd with respect to v dd . . . . . . . . . . . . . .33 fig 24. driver timing waveforms . . . . . . . . . . . . . . . . . . .35 fig 25. i 2 c-bus timing waveforms . . . . . . . . . . . . . . . . . .35 fig 26. cascaded pca85262 configuration. . . . . . . . . . .37 fig 27. synchronization of the cascade for the various pca85262 drive modes . . . . . . . . . . . . . . . . . . . .38 fig 28. package outline sot362-1 (tssop48) of PCA85262ATT . . . . . . . . . . . . . . . . . . . . . . . . . . .40 fig 29. temperature profiles for large and small components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 fig 30. footprint information for reflow soldering of sot362-1 (tssop48) of PCA85262ATT . . . . . .45 nxp semiconductors pca85262 32 x 4 automotive lcd driv er for low multiplex rates ? nxp b.v. 2014. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 11 february 2014 document identifier: pca85262 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 29. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 functional description . . . . . . . . . . . . . . . . . . . 5 7.1 commands of pca85262 . . . . . . . . . . . . . . . . . 5 7.1.1 command: mode-set . . . . . . . . . . . . . . . . . . . . 5 7.1.2 command: load-data-pointer . . . . . . . . . . . . . . 6 7.1.3 command: device-select . . . . . . . . . . . . . . . . . 6 7.1.4 command: bank-select. . . . . . . . . . . . . . . . . . . 6 7.1.5 command: blink-select . . . . . . . . . . . . . . . . . . . 7 7.1.5.1 blinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.2 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.3 possible display configurations . . . . . . . . . . . . 9 7.3.1 lcd bias generator . . . . . . . . . . . . . . . . . . . . 10 7.3.2 display register . . . . . . . . . . . . . . . . . . . . . . . . 10 7.3.3 lcd voltage selector . . . . . . . . . . . . . . . . . . . 10 7.3.3.1 electro-optical performance . . . . . . . . . . . . . . 12 7.3.4 lcd drive mode waveforms . . . . . . . . . . . . . . 14 7.3.4.1 static drive mode . . . . . . . . . . . . . . . . . . . . . . 14 7.3.4.2 1:2 multiplex drive mode. . . . . . . . . . . . . . . . . 15 7.3.4.3 1:3 multiplex drive mode. . . . . . . . . . . . . . . . . 17 7.3.4.4 1:4 multiplex drive mode. . . . . . . . . . . . . . . . . 18 7.4 oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.4.1 internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.4.2 external clock . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.4.3 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.5 backplane and segment outputs . . . . . . . . . . 19 7.5.1 backplane outputs . . . . . . . . . . . . . . . . . . . . . 19 7.5.2 segment outputs. . . . . . . . . . . . . . . . . . . . . . . 19 7.6 display ram . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.6.1 data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.6.2 subaddress counter . . . . . . . . . . . . . . . . . . . . 22 7.6.3 ram addressing in cascaded applications . . . 22 7.6.4 ram writing in 1:3 multiplex drive mode. . . . . 22 7.6.5 bank selection . . . . . . . . . . . . . . . . . . . . . . . . 23 7.6.5.1 output bank selector . . . . . . . . . . . . . . . . . . . 23 7.6.5.2 input bank selector . . . . . . . . . . . . . . . . . . . . . 24 7.6.5.3 ram bank switching . . . . . . . . . . . . . . . . . . . . 24 8 characteristics of the i 2 c-bus . . . . . . . . . . . . 26 8.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.2 start and stop conditions. . . . . . . . . . . . . 26 8.3 system configuration . . . . . . . . . . . . . . . . . . . 26 8.4 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.5 i 2 c-bus controller . . . . . . . . . . . . . . . . . . . . . . 28 8.6 input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.7 i 2 c-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 28 9 internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 30 10 safety notes. . . . . . . . . . . . . . . . . . . . . . . . . . . 31 11 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 31 12 static characteristics . . . . . . . . . . . . . . . . . . . 32 13 dynamic characteristics. . . . . . . . . . . . . . . . . 34 14 application information . . . . . . . . . . . . . . . . . 35 14.1 cascaded operation. . . . . . . . . . . . . . . . . . . . 35 15 test information . . . . . . . . . . . . . . . . . . . . . . . 39 15.1 quality information . . . . . . . . . . . . . . . . . . . . . 39 16 package outline. . . . . . . . . . . . . . . . . . . . . . . . 40 17 handling information . . . . . . . . . . . . . . . . . . . 41 18 packing information . . . . . . . . . . . . . . . . . . . . 42 18.1 tape and reel information . . . . . . . . . . . . . . . 42 19 soldering of smd packages . . . . . . . . . . . . . . 42 19.1 introduction to soldering. . . . . . . . . . . . . . . . . 42 19.2 wave and reflow soldering. . . . . . . . . . . . . . . 42 19.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . 42 19.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . 43 20 footprint information . . . . . . . . . . . . . . . . . . . 44 21 appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 21.1 lcd segment driver selection . . . . . . . . . . . . 46 22 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 48 23 references. . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 24 revision history . . . . . . . . . . . . . . . . . . . . . . . 50 25 legal information . . . . . . . . . . . . . . . . . . . . . . 51 25.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 51 25.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 25.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 51 25.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 52 26 contact information . . . . . . . . . . . . . . . . . . . . 52 27 tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 28 figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 29 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 |
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